1. Field of Invention
This invention relates generally to high-speed serial bus operation, and more specifically to low latency techniques applied to a multi-link serial bus architecture.
2. Art Background
A data bus is commonly used in data processing devices such as a computer to send and receive data from a plurality of devices. Data buses have been constructed around a serial or a parallel architecture. For example, a serial data bus can connect together a printer, a scanner, a storage device, and a wireless transceiver to facilitate communication between devices. Such a configuration of devices connected sequentially is known in the art as a daisy chain.
A controller is used to send data to a first device on the serial data bus. Data prepared for transmission on a serial data bus can be referred to in the art as a packet of data. The packet of data typically has an address corresponding to a unique device on the serial data bus. The data stream transmitted onto the serial data bus can consist of a sequence of packets randomly addressed to different devices distributed along the serial data bus.
In serial data bus architecture, a plurality of bits (a bit stream) is transmitted sequentially in time across a data transmission path. Thus, a first bit is followed by a second bit, etc., eventually completing the transmission of a first data word and then a second data word. Data transfer accomplished using serial data bus architecture has traditionally suffered from high latency. Current serial data bus protocol requires the transmission of the serial data word or packet to the first device in the daisy chain and then from the first device to the second device in the daisy chain, progressing down the serial data bus to the last device. According to present bus architecture, each device along the serial data bus reads the packet of data, checks it for errors and then retransmits the packet to the next device if the packet address did not match the given device address. If an error is found, the device notifies the controller along a second serial data transmission path and the controller responds to the error condition.
Such a protocol suffers from high latency, since each device must read the data and perform an error check on the packet of data, even if the packet of data is not addressed to the device performing the check.